Compaq 21264 User Manual

Compaq Computer Corporation Shrewsbury, MassachusettsAlpha 21264/EV67 Microprocessor Hardware Reference ManualOrder Number: D

xAlpha 21264/EV67 Hardware Reference ManualD.26 Restriction 30 : HW_MTPR and HW_MFPR to the Cbox CSR . . . . . . . . . . . . . . . . . . . . . . . D–

4–12 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualCache CoherencyRdBlkModx ReadDataReadDataSharedReadDataShared/DirtyThe cac

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–13Cache CoherencyThe 21264/EV67 sends a WrVictimBlk command to the system wh

4–14 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualLock Mechanism1. When the Mbox requests a Dcache fill, the Cbox uses the C

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–15Lock Mechanism4.6.1 In-Order Processing of LDx_L/STx_C InstructionsThe 212

4–16 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualSystem PortIf the ChangeToDirty command succeeds, the STx_C enters the wri

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–17System PortFigure 4–4 System Interface Signals4.7.1 System Port PinsTable

4–18 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualSystem Port4.7.2 Programming the System Interface ClocksThe system forward

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–19System PortTable 4–9 lists the program values for CSR SYS_FRAME_LD_VECTOR[

4–20 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualSystem Port4.7.3.2 Page Hit ModeTable 4–11 shows the command format for pa

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–21System PortSystem designers can minimize pin count for systems with a smal

Alpha 21264/EV67 Hardware Reference ManualxiFigures2–1 21264/EV67 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–22 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualSystem PortReadBlkMod 10001 Memory read with modify intent.ReadBlkI 10010

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–23System PortTable 4–14 footnotes:1. Systems can optionally enable MB instru

4–24 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualSystem PortSystems that require an explicit indication of ChangeToDirty st

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–25System PortTable 4–18 describes the ProbeResponse command fields. The sys

4–26 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualSystem Port• There is no mechanism for the system to reject a 21264/EV67-t

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–27System PortTable 4–20 describes the system-to-21264/EV67 probe commands fi

4–28 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualSystem PortThe 21264/EV67 holds pending probe commands in a 8-entry deep p

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–29System PortTable 4–24 describes the SysDc[4:0] field.The A bit in the firs

4–30 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualSystem PortThe ChangeToDirtySuccess and ChangeToDirtyFail commands cannot

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–31System PortIf both the sender and the receiver are sampling at the same ra

xiiAlpha 21264/EV67 Hardware Reference Manual5–34 Dcache Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–32 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualSystem PortThe command precedes data by at least one SYSCLK period. Table

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–33System PortTable 4–26 shows four example configurations and shows their us

4–34 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualSystem PortTable 4–27 lists information for the four timing examples. In T

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–35System Port1. The SysDataInValid_L signal must be asserted for both cycle

4–36 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualSystem PortFigure 4–6 SysFillValid_L Timing4.7.8.6 Data Wrapping All data

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–37System Portpoint is the QW pointed to by the 21264/EV67; however, some sy

4–38 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualSystem PortTable 4–31 defines the wrap order for double-pumped data transf

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–39System PortTable 4–32 shows each 21264/EV67 command, with NXM addresses, a

4–40 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualSystem Port4.7.10 Ordering of System Port TransactionsThis section describ

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–41System Port• Probes that invalidate locked blocks do not generate a ReadBl

Alpha 21264/EV67 Hardware Reference ManualxiiiTables1–1 Integer Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–42 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualBcache Port4.7.10.2 System Probes and SysDc CommandsOrdering of cache tran

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–43Bcache PortThe Bcache supports the following multiples of the GCLK period:

4–44 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualBcache Port4.8.2 Bcache ClockingFor clocking, the Bcache port pins can be

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–45Bcache PortBcTagShared_HBcTagValid_H3. The Bcache clock pins (BcDataOutClk

4–46 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualBcache Port3. BC_FDBK_EN[7:0]To program these three CSRs, the programmer m

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–47Bcache PortIn addition to programming the clock CSRs, the data-sample/driv

4–48 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualBcache Porthave been programmed for the Bcache clock period, and with sati

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–49Bcache Portpriate programming of the Bcache clock period and delay paramet

4–50 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualBcache PortRatio The number of GCLK cycles per peak Bcache bandwidth trans

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–51Bcache PortThe Relationship Between Write-to-Read — BC_WR_RD_BUBBLES and

xivAlpha 21264/EV67 Hardware Reference Manual4–34 Rules for System Control of Cache Status Update Order. . . . . . . . . . . . . . . . . . . . . . . .

4–52 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualBcache PortWhen the Cbox CSR BC_BANK_ENABLE[0] is not set, the unused BcAd

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–53Bcache PortTable 4–46 lists the combination of control pin assertion for R

4–54 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualInterrupts4.8.5 Bcache BankingBcache banking is possible by decoding the i

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–1 5Internal Processor RegistersThis chapter describes 21264/EV67 internal pro

5–2 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualInstruction VA format IVA_FORM 0000 0111 5 RO 0L 3Current mode CM 0000 1001

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–3Ebox IPRs5.1 Ebox IPRsThis section describes the internal processor register

5–4 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualEbox IPRsTable 5–2 describes the CC_CTL register fields.5.1.3 Virtual Addres

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–5Ebox IPRsTable 5–3 describes the virtual address control register fields.5.1

5–6 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualIbox IPRsFigure 5–6 Virtual Address Format Register (VA_48 = 1, VA_FORM_32 =

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–7Ibox IPRsFigure 5–9 ITB PTE Array Write Register5.2.3 ITB Invalidate All Pro

Alpha 21264/EV67 Hardware Reference Manualxv7–6 Effect on IPRs After Transition Through Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . .

5–8 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualIbox IPRs5.2.6 ProfileMe PC Register – PMPCThe ProfileMe PC register (PMPC)

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–9Ibox IPRs5.2.8 Instruction Virtual Address Format Register — IVA_FORMThe ins

5–10 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualIbox IPRsFigure 5–16 Interrupt Enable and Current Processor Mode RegisterTa

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–11Ibox IPRsFigure 5–17 Software Interrupt Request RegisterTable 5–6 describes

5–12 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualIbox IPRsTable 5–7 describes the interrupt summary register fields.5.2.12 H

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–13Ibox IPRsTable 5–8 describes the hardware interrupt clear register fields.5

5–14 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualIbox IPRsFigure 5–20 Exception Summary RegisterTable 5–9 describes the exce

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–15Ibox IPRs5.2.14 PAL Base Register – PAL_BASEThe PAL base register (PAL_BASE

5–16 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualIbox IPRsFigure 5–22 Ibox Control RegisterTable 5–11 describes the Ibox con

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–17Ibox IPRsMCHK_EN [21] RW,0 Machine check enable — set to enable machine che

5–18 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualIbox IPRs5.2.16 Ibox Status Register – I_STATThe Ibox status register (I_ST

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–19Ibox IPRsFigure 5–23 Ibox Status RegisterTable 5–12 describes the Ibox stat

5–20 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualIbox IPRsTRAP TYPE[3:0][37:34] RO ProfileMe Trap Types.If the profiled inst

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–21Ibox IPRs5.2.17 Icache Flush Register – IC_FLUSHThe Icache flush register (

5–22 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualIbox IPRsFigure 5–24 Process Context RegisterTable 5–14 describes the proce

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–23Ibox IPRs5.2.22 Performance Counter Control Register – PCTR_CTLThe performa

5–24 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualIbox IPRsTable 5–15 describes the performance counter control register fiel

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–25Mbox IPRs5.3 Mbox IPRsThis section describes the internal processor registe

5–26 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualMbox IPRs5.3.2 DTB PTE Array Write Registers 0 and 1 – DTB_PTE0, DTB_PTE1Th

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–27Mbox IPRsTable 5–17 describes the DTB_ALTMODE register fields.5.3.4 Dstream

Alpha 21264/EV67 Hardware Reference Manualxvii PrefaceAudienceThis manual is for system designers and programmers who use the Alpha 21264/EV67 micropr

5–28 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualMbox IPRs5.3.7 Dstream TB Address Space Number Registers 0 and 1 – DTB_ASN0

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–29Mbox IPRsNote: The Ra field of the instruction that triggered the error can

5–30 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualMbox IPRsTable 5–19 describes the Mbox control register fields.Note: Superp

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–31Mbox IPRsFigure 5–33 Dcache Control RegisterTable 5–20 describes the Dcache

5–32 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualCbox CSRs and IPRsFigure 5–34 Dcache Status RegisterTable 5–21 describes th

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–33Cbox CSRs and IPRs5.4.1 Cbox Data Register – C_DATAFigure 5–35 shows the Cb

5–34 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualCbox CSRs and IPRs• Only a brief description of each CSR is given. The func

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–35Cbox CSRs and IPRsDUP_TAG_ENABLE Duplicate CSR.SKEWED_FILL_MODE Duplicate C

5–36 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualCbox CSRs and IPRsBC_TAG_DDM_RISE_EN[0] Enables the update of the 21264/EV6

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–37Cbox CSRs and IPRsSYS_DDM_FALL_EN Duplicate CSR.SYS_DDM_RISE_EN Duplicate C

xviiiAlpha 21264/EV67 Hardware Reference ManualAppendix C, Serial Icache Load Predecode Values, provides a pointer to the Alpha Motherboards Software

5–38 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualCbox CSRs and IPRs5.4.4 Cbox WRITE_MANY Chain DescriptionThe WRITE_MANY cha

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–39Cbox CSRs and IPRsTable 5–25 describes the Cbox WRITE_MANY chain order from

5–40 Internal Processor RegistersAlpha 21264/EV67 Hardware Reference ManualCbox CSRs and IPRs; SET_DIRTY_ENABLE = 6; BC_BANK_ENABLE = 1; BC_WRT_STS =

Alpha 21264/EV67 Hardware Reference ManualInternal Processor Registers 5–41Cbox CSRs and IPRs5.4.5 Cbox Read Register (IPR) DescriptionThe Cbox read r

Alpha 21264/EV67 Hardware Reference ManualPrivileged Architecture Library Code 6–1 6Privileged Architecture Library CodeThis chapter describes the 212

6–2 Privileged Architecture Library CodeAlpha 21264/EV67 Hardware Reference ManualPALmode Environment• There are some necessary support functions that

Alpha 21264/EV67 Hardware Reference ManualPrivileged Architecture Library Code 6–3Required PALcode Function CodesWhen executing in PALmode, there are

6–4 Privileged Architecture Library CodeAlpha 21264/EV67 Hardware Reference ManualOpcodes Reserved for PALcodeFigure 6–1 HW_LD Instruction FormatTable

Alpha 21264/EV67 Hardware Reference ManualPrivileged Architecture Library Code 6–5Opcodes Reserved for PALcodeTable 6–4 describes the HW_ST instructio

Alpha 21264/EV67 Hardware Reference ManualxixTerminology and ConventionsThis section defines the abbreviations, terminology, and other conventions us

6–6 Privileged Architecture Library CodeAlpha 21264/EV67 Hardware Reference ManualOpcodes Reserved for PALcodeFigure 6–3 HW_RET Instruction FormatTabl

Alpha 21264/EV67 Hardware Reference ManualPrivileged Architecture Library Code 6–7Internal Processor Register Access MechanismsTable 6–6 describes the

6–8 Privileged Architecture Library CodeAlpha 21264/EV67 Hardware Reference ManualInternal Processor Register Access Mechanisms6.5.1 IPR Scoreboard Bi

Alpha 21264/EV67 Hardware Reference ManualPrivileged Architecture Library Code 6–9Internal Processor Register Access Mechanisms6.5.3 Hardware Structur

6–10 Privileged Architecture Library CodeAlpha 21264/EV67 Hardware Reference ManualInternal Processor Register Access MechanismsFor convenience of imp

Alpha 21264/EV67 Hardware Reference ManualPrivileged Architecture Library Code 6–11PALshadow Registers6.5.6 Correct Ordering of Explicit Readers Follo

6–12 Privileged Architecture Library CodeAlpha 21264/EV67 Hardware Reference ManualPALcode Entry Points3. Correct actions must occur when the FPCR is

Alpha 21264/EV67 Hardware Reference ManualPrivileged Architecture Library Code 6–13PALcode Entry PointsEach CALL_PAL instruction includes a function f

6–14 Privileged Architecture Library CodeAlpha 21264/EV67 Hardware Reference ManualTranslation Buffer (TB) Fill Flows6.9 Translation Buffer (TB) Fill

Alpha 21264/EV67 Hardware Reference ManualPrivileged Architecture Library Code 6–15Translation Buffer (TB) Fill Flows hw_mtprp4, <EV6__DTB_PTE0 !

September 2000The information in this publication is subject to change without notice.COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR

xxAlpha 21264/EV67 Hardware Reference Manual• Sign extensionSEXT(x) means x is sign-extended to the required size.AddressesUnless otherwise noted, all

6–16 Privileged Architecture Library CodeAlpha 21264/EV67 Hardware Reference ManualTranslation Buffer (TB) Fill Flows• The conditional branch is place

Alpha 21264/EV67 Hardware Reference ManualPrivileged Architecture Library Code 6–17Performance Counter Supportsrl r4, #OSF_PTE__PFN__S, r6 ; (xU) shif

6–18 Privileged Architecture Library CodeAlpha 21264/EV67 Hardware Reference ManualPerformance Counter SupportProfileMe mode, supports a new way of st

Alpha 21264/EV67 Hardware Reference ManualPrivileged Architecture Library Code 6–19Performance Counter SupportThe legal range for PCTR0 when writing t

6–20 Privileged Architecture Library CodeAlpha 21264/EV67 Hardware Reference ManualPerformance Counter Support6.10.2.3 Aggregate Counting Mode Descrip

Alpha 21264/EV67 Hardware Reference ManualPrivileged Architecture Library Code 6–21Performance Counter SupportThe CMOV instruction is decomposed into

6–22 Privileged Architecture Library CodeAlpha 21264/EV67 Hardware Reference ManualPerformance Counter SupportFor instructions that cause a trap, the

Alpha 21264/EV67 Hardware Reference ManualPrivileged Architecture Library Code 6–23Performance Counter Support6.10.3.3 ProfileMe Counting Mode Descrip

6–24 Privileged Architecture Library CodeAlpha 21264/EV67 Hardware Reference ManualPerformance Counter Support6.10.3.4 Counter Modes for ProfileMe Mod

Alpha 21264/EV67 Hardware Reference ManualInitialization and Configuration 7–1 7Initialization and ConfigurationThis chapter provides information on 2

Alpha 21264/EV67 Hardware Reference ManualxxiData UnitsThe following data unit terminology is used throughout this manual.Do Not Care (X)A capital X r

7–2 Initialization and ConfigurationAlpha 21264/EV67 Hardware Reference ManualPower-Up Reset Flow and the Reset_L and DCOK_H Pins1. The clock forwardi

Alpha 21264/EV67 Hardware Reference ManualInitialization and Configuration 7–3Power-Up Reset Flow and the Reset_L and DCOK_H PinsFigure 7–1 Power-Up T

7–4 Initialization and ConfigurationAlpha 21264/EV67 Hardware Reference ManualPower-Up Reset Flow and the Reset_L and DCOK_H PinsIn addition, as power

Alpha 21264/EV67 Hardware Reference ManualInitialization and Configuration 7–5Power-Up Reset Flow and the Reset_L and DCOK_H PinsTable 7–3 summarizes

7–6 Initialization and ConfigurationAlpha 21264/EV67 Hardware Reference ManualPower-Up Reset Flow and the Reset_L and DCOK_H Pins7.1.3 PLL Ramp UpAfte

Alpha 21264/EV67 Hardware Reference ManualInitialization and Configuration 7–7Power-Up Reset Flow and the Reset_L and DCOK_H PinsAs BiST completes, th

7–8 Initialization and ConfigurationAlpha 21264/EV67 Hardware Reference ManualFault Reset Flow7.2 Fault Reset FlowThe fault reset sequence of operatio

Alpha 21264/EV67 Hardware Reference ManualInitialization and Configuration 7–9Energy Star Certification and Sleep Mode FlowFigure 7–2 Fault Reset Sequ

7–10 Initialization and ConfigurationAlpha 21264/EV67 Hardware Reference ManualEnergy Star Certification and Sleep Mode FlowAfter the PLL has finished

Alpha 21264/EV67 Hardware Reference ManualInitialization and Configuration 7–11Warm Reset FlowFigure 7–3 Sleep Mode Sequence of Operation Table 7–7 de

xxiiAlpha 21264/EV67 Hardware Reference ManualAlphaSignal[n:n] Boldface, mixed-case type denotes signal names that are assigned internal and external

7–12 Initialization and ConfigurationAlpha 21264/EV67 Hardware Reference ManualArray InitializationThe 21264/EV67 waits until Reset_L is deasserted be

Alpha 21264/EV67 Hardware Reference ManualInitialization and Configuration 7–13Initialization Mode ProcessingExcept for INIT_MODE, all the CSR registe

7–14 Initialization and ConfigurationAlpha 21264/EV67 Hardware Reference ManualExternal Interface InitializationSweepMemory: ;Write good parity/ecc to

Alpha 21264/EV67 Hardware Reference ManualInitialization and Configuration 7–15Internal Processor Register Power-Up Reset StateITB_IAP ITB invalidate-

7–16 Initialization and ConfigurationAlpha 21264/EV67 Hardware Reference ManualIEEE 1149.1 Test Port Reset7.9 IEEE 1149.1 Test Port ResetSignal Trst_

Alpha 21264/EV67 Hardware Reference ManualInitialization and Configuration 7–17Reset State MachineFigure 7–5 21264/EV67 Reset State Machine State Diag

7–18 Initialization and ConfigurationAlpha 21264/EV67 Hardware Reference ManualReset State MachineRAMP2 Triggered by the duration counter reaching 410

Alpha 21264/EV67 Hardware Reference ManualInitialization and Configuration 7–19Phase-Lock Loop (PLL) Functional Description7.11 Phase-Lock Loop (PLL)

7–20 Initialization and ConfigurationAlpha 21264/EV67 Hardware Reference ManualPhase-Lock Loop (PLL) Functional DescriptionTable 7–12 shows the allowa

Alpha 21264/EV67 Hardware Reference ManualError Detection and Error Handling 8–1 8Error Detection and Error HandlingThis chapter gives an overview of

Alpha 21264/EV67 Hardware Reference ManualxxiiiX Do not care. A capital X represents any valid value.

8–2 Error Detection and Error HandlingAlpha 21264/EV67 Hardware Reference ManualData Error Correction Code8.1 Data Error Correction CodeThe 21264/EV67

Alpha 21264/EV67 Hardware Reference ManualError Detection and Error Handling 8–3Dcache Data Single-Bit Correctable ECC Error3. The virtual address ass

8–4 Error Detection and Error HandlingAlpha 21264/EV67 Hardware Reference ManualDcache Store Second Error– C_ADDR contains bits [19:6] of the Dcache a

Alpha 21264/EV67 Hardware Reference ManualError Detection and Error Handling 8–5Bcache Tag Parity Error• C_STAT[DC_PERR] is set.• C_ADDR contains bits

8–6 Error Detection and Error HandlingAlpha 21264/EV67 Hardware Reference ManualBcache Data Single-Bit Correctable ECC Error8.8.2 Dcache Fill from Bca

Alpha 21264/EV67 Hardware Reference ManualError Detection and Error Handling 8–7Memory/System Port Single-Bit Data Correctable ECC ErrorThe Bcache acc

8–8 Error Detection and Error HandlingAlpha 21264/EV67 Hardware Reference ManualBcache Data Single-Bit Correctable ECC Error on a ProbeIf the quadword

Alpha 21264/EV67 Hardware Reference ManualError Detection and Error Handling 8–9Double-Bit Fill Errors8.11 Double-Bit Fill ErrorsDouble-bit errors for

8–10 Error Detection and Error HandlingAlpha 21264/EV67 Hardware Reference ManualError Case SummaryDcache single-bit ECC error onspeculative loadCRD D

Alpha 21264/EV67 Hardware Reference ManualError Detection and Error Handling 8–11Error Case SummaryBcache double-bit error on Dcache fillMCHK1C_STAT[D

Alpha 21264/EV67 Hardware Reference ManualElectrical Data 9–1 9Electrical DataThis chapter describes the electrical characteristics of the 21264/EV67

9–2 Electrical DataAlpha 21264/EV67 Hardware Reference ManualDC Characteristics9.2 DC CharacteristicsThis section contains the dc characteristics for

Alpha 21264/EV67 Hardware Reference ManualElectrical Data 9–3DC CharacteristicsNote: Current out of a 21264/EV67 pin is represented by a – symbol whil

9–4 Electrical DataAlpha 21264/EV67 Hardware Reference ManualDC CharacteristicsTable 9–7 Pin Type: Open-Drain Output Driver (O_OD)Parameter Symbol Des

Alpha 21264/EV67 Hardware Reference ManualElectrical Data 9–5Power Supply Sequencing and Avoiding Potential Failure Mechanisms9.3 Power Supply Sequenc

9–6 Electrical DataAlpha 21264/EV67 Hardware Reference ManualAC Characteristicsthe tester environment and does not need to be disabled. EV6Clk_L and E

Alpha 21264/EV67 Hardware Reference ManualElectrical Data 9–7AC Characteristics• The input voltage swing is Vref ± 0.40 Volts.• All output skew data i

9–8 Electrical DataAlpha 21264/EV67 Hardware Reference ManualAC CharacteristicsBcTagShared_H B_DA_PP BcTagInClk_H 400 ps 400 ps NA NA 1.0 V/nsBcTagVal

Alpha 21264/EV67 Hardware Reference ManualElectrical Data 9–9AC Characteristics6The TSkew value applies only when the BC_CLK_DELAY[0:1] entry in the C

Alpha 21264/EV67 Hardware Reference ManualIntroduction 1–1 1IntroductionThis chapter provides a brief introduction to the Alpha architecture, Compaq’s

Alpha 21264/EV67 Hardware Reference ManualThermal Management 10–1 10Thermal ManagementThis chapter describes the 21264/EV67 thermal management and the

10–2 Thermal ManagementAlpha 21264/EV67 Hardware Reference ManualOperating TemperatureTable 10–2 lists the values for the center of heat-sink-to-ambie

Alpha 21264/EV67 Hardware Reference ManualThermal Management 10–3Heat Sink Specifications10.2 Heat Sink SpecificationsThree heat sink types are specif

10–4 Thermal ManagementAlpha 21264/EV67 Hardware Reference ManualHeat Sink SpecificationsFigure 10–1 Type 1 Heat Sink25.4 mm(1.0 in)32.5 mm(1.280 in)8

Alpha 21264/EV67 Hardware Reference ManualThermal Management 10–5Heat Sink SpecificationsFigure 10–2 shows the heat sink type 2, along with its approx

10–6 Thermal ManagementAlpha 21264/EV67 Hardware Reference ManualHeat Sink SpecificationsFigure 10–3 shows heat sink type 3, along with its approximat

Alpha 21264/EV67 Hardware Reference ManualThermal Management 10–7Thermal Design Considerations10.3 Thermal Design ConsiderationsFollow these guideline

Alpha 21264/EV67 Hardware Reference ManualTestability and Diagnostics 11–1 11Testability and DiagnosticsThis chapter describes the 21264/EV67 user-or

1–2 IntroductionAlpha 21264/EV67 Hardware Reference ManualThe Architecturedirect access to low-level hardware functions. PALcode supports optimization

11–2 Testability and DiagnosticsAlpha 21264/EV67 Hardware Reference ManualSROM/Serial Diagnostic Terminal Port11.2 SROM/Serial Diagnostic Terminal Por

Alpha 21264/EV67 Hardware Reference ManualTestability and Diagnostics 11–3IEEE 1149.1 PortOn the receive side, while in native mode, any transition o

11–4 Testability and DiagnosticsAlpha 21264/EV67 Hardware Reference ManualTestStat_H PinFigure 11–1 TAP Controller State Machine11.4 TestStat_H PinThe

Alpha 21264/EV67 Hardware Reference ManualTestability and Diagnostics 11–5Power-Up Self-Test and InitializationFigure 11–2 TestStat_H Pin Timing Durin

11–6 Testability and DiagnosticsAlpha 21264/EV67 Hardware Reference ManualPower-Up Self-Test and InitializationIn the SROM represented in Figure 11–4,

Alpha 21264/EV67 Hardware Reference ManualTestability and Diagnostics 11–7Notes on IEEE 1149.1 Operation and ComplianceThe instruction cache lines are

Alpha 21264/EV67 Hardware Reference ManualAlpha Instruction Set A–1 AAlpha Instruction SetThis appendix provides a summary of the Alpha instruction se

A–2 Alpha Instruction SetAlpha 21264/EV67 Hardware Reference ManualAlpha Instruction SummaryQualifiers for operate instructions are shown in Table A–2

Alpha 21264/EV67 Hardware Reference ManualAlpha Instruction Set A–3Alpha Instruction SummaryBSR Mbr 34 Branch to subroutineCALL_PAL Pcd 00 Trap to PAL

Alpha 21264/EV67 Hardware Reference ManualIntroduction 1–321264/EV67 Microprocessor Features1.2 21264/EV67 Microprocessor FeaturesThe 21264/EV67 micro

A–4 Alpha Instruction SetAlpha 21264/EV67 Hardware Reference ManualAlpha Instruction SummaryCVTGQ F-P 15.0AF Convert G_floating to quadwordCVTLQ F-P

Alpha 21264/EV67 Hardware Reference ManualAlpha Instruction Set A–5Alpha Instruction SummaryFCMOVGT F-P 17.02F FCMOVE if > zeroFCMOVLE F-P 17.02

A–6 Alpha Instruction SetAlpha 21264/EV67 Hardware Reference ManualAlpha Instruction SummaryLDS Mem 22 Load S_floatingLDT Mem 23 Load T_floatingLDWU M

Alpha 21264/EV67 Hardware Reference ManualAlpha Instruction Set A–7Alpha Instruction SummaryPKWB Opr 1C.36 Pack words to bytesRC Mfc 18.E000 Read and

A–8 Alpha Instruction SetAlpha 21264/EV67 Hardware Reference ManualReserved OpcodesA.2 Reserved OpcodesThis section describes the opcodes that are res

Alpha 21264/EV67 Hardware Reference ManualAlpha Instruction Set A–9IEEE Floating-Point InstructionsA.2.2 Opcodes Reserved for PALcodeTable A–4 lists t

A–10 Alpha Instruction SetAlpha 21264/EV67 Hardware Reference ManualIEEE Floating-Point InstructionsSQRTS 08B 00B 04B 0CB 18B 10B 14B 1CBSQRTT 0AB 02B

Alpha 21264/EV67 Hardware Reference ManualAlpha Instruction Set A–11VAX Floating-Point InstructionsProgramming Note:In order to use CMPTxx with softwa

A–12 Alpha Instruction SetAlpha 21264/EV67 Hardware Reference ManualOpcode SummaryTable A–7 Independent Floating-Point Instruction Function CodesA.6 O

Alpha 21264/EV67 Hardware Reference ManualAlpha Instruction Set A–13Required PALcode Function CodesTable A–9 explains the symbols used in Table A–8.A.

1–4 IntroductionAlpha 21264/EV67 Hardware Reference Manual21264/EV67 Microprocessor Features• An onchip, duplicate tag array used to maintain level 2

A–14 Alpha Instruction SetAlpha 21264/EV67 Hardware Reference ManualIEEE Floating-Point ConformanceA.8 IEEE Floating-Point ConformanceThe 21264/EV67 s

Alpha 21264/EV67 Hardware Reference ManualAlpha Instruction Set A–15IEEE Floating-Point ConformanceThe 21264/EV67 does not produce a denormal result f

A–16 Alpha Instruction SetAlpha 21264/EV67 Hardware Reference ManualIEEE Floating-Point ConformanceMULx INPUTInf operand ±Inf (none)QNaN operand QNaN

Alpha 21264/EV67 Hardware Reference ManualAlpha Instruction Set A–17IEEE Floating-Point ConformanceSee Section 2.14 for information about the floating

Alpha 21264/EV67 Hardware Reference Manual21264/EV67 Boundary-Scan Register B–1 B21264/EV67 Boundary-Scan RegisterThis appendix contains the BSDL desc

B–2 21264/EV67 Boundary-Scan RegisterAlpha 21264/EV67 Hardware Reference ManualBoundary-Scan Register SysDataInClk_H :in bit_vect

Alpha 21264/EV67 Hardware Reference Manual21264/EV67 Boundary-Scan Register B–3Boundary-Scan Register " AB38, AC3

B–4 21264/EV67 Boundary-Scan RegisterAlpha 21264/EV67 Hardware Reference ManualBoundary-Scan Register "NoConnect_0 : BB14, &

Alpha 21264/EV67 Hardware Reference Manual21264/EV67 Boundary-Scan Register B–5Boundary-Scan Register "BcLoad_L : 124 ,

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–1 2Internal ArchitectureThis chapter provides both an overview of the 21264/EV67 mic

B–6 21264/EV67 Boundary-Scan RegisterAlpha 21264/EV67 Hardware Reference ManualBoundary-Scan Register "VSS : (44 , 259

Alpha 21264/EV67 Hardware Reference Manual21264/EV67 Boundary-Scan Register B–7Boundary-Scan Register " 364 ( BC_2, SromClk_H, OUTPUT2,

B–8 21264/EV67 Boundary-Scan RegisterAlpha 21264/EV67 Hardware Reference ManualBoundary-Scan Register " 299 ( BC_2, BcData_H(83), BIDIR,

Alpha 21264/EV67 Hardware Reference Manual21264/EV67 Boundary-Scan Register B–9Boundary-Scan Register " 234 ( BC_2, BcData_H(3) , BIDIR,

B–10 21264/EV67 Boundary-Scan RegisterAlpha 21264/EV67 Hardware Reference ManualBoundary-Scan Register " 169 ( BC_2, BcAdd_H(21), OUTPUT2,

Alpha 21264/EV67 Hardware Reference Manual21264/EV67 Boundary-Scan Register B–11Boundary-Scan Register " 104 ( BC_2, BcData_H(47), BIDIR,

B–12 21264/EV67 Boundary-Scan RegisterAlpha 21264/EV67 Hardware Reference ManualBoundary-Scan Register " 39 ( BC_2, BcData_H(127), BIDIR,

Alpha 21264/EV67 Hardware Reference ManualSerial Icache Load Predecode Values C–1 CSerial Icache Load Predecode ValuesSee the Alpha Motherboards Softw

Alpha 21264/EV67 Hardware Reference ManualPALcode Restrictions and Guidelines D–1 DPALcode Restrictions and GuidelinesD.1 Restriction 1 : Reset Seq

Alpha 21264/EV67 Hardware Reference Manualiii Table of ContentsPreface1 Introduction1.1 The Architecture . . . . . . . . . . . . . . . . . . . . . . .

2–2 Internal ArchitectureAlpha 21264/EV67 Hardware Reference Manual21264/EV67 Microarchitecture• Floating-point execution unit (Fbox)• Onchip caches (

D–2 PALcode Restrictions and GuidelinesAlpha 21264/EV67 Hardware Reference ManualRestriction 1 : Reset Sequence Required by Retire Logic and Mapperadd

Alpha 21264/EV67 Hardware Reference ManualPALcode Restrictions and Guidelines D–3Restriction 1 : Reset Sequence Required by Retire Logic and Mapperadd

D–4 PALcode Restrictions and GuidelinesAlpha 21264/EV67 Hardware Reference ManualRestriction 1 : Reset Sequence Required by Retire Logic and Mapper**

Alpha 21264/EV67 Hardware Reference ManualPALcode Restrictions and Guidelines D–5Restriction 1 : Reset Sequence Required by Retire Logic and Mapperadd

D–6 PALcode Restrictions and GuidelinesAlpha 21264/EV67 Hardware Reference ManualRestriction 1 : Reset Sequence Required by Retire Logic and Mapperbr

Alpha 21264/EV67 Hardware Reference ManualPALcode Restrictions and Guidelines D–7Restriction 1 : Reset Sequence Required by Retire Logic and Mappermtp

D–8 PALcode Restrictions and GuidelinesAlpha 21264/EV67 Hardware Reference ManualRestriction 2 : No Multiple Writers to IPRs in Same Scoreboard Groupb

Alpha 21264/EV67 Hardware Reference ManualPALcode Restrictions and Guidelines D–9Guideline 6 : Avoid Consecutive Read-Modify-Write-Read-Modify-WriteD.

D–10 PALcode Restrictions and GuidelinesAlpha 21264/EV67 Hardware Reference ManualRestriction 9 : PALmode Istream Address RangesBad_interrupt_flow_ent

Alpha 21264/EV67 Hardware Reference ManualPALcode Restrictions and Guidelines D–11Restriction 11: Ibox IPR Update SynchronizationD.8 Restriction 11:

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–321264/EV67 MicroarchitectureFigure 2–1 21264/EV67 Block Diagram 2.1.1.2 Branch Pred

D–12 PALcode Restrictions and GuidelinesAlpha 21264/EV67 Hardware Reference ManualGuideline 16 : JSR-BAD VAD.12 Guideline 16 : JSR-BAD VA A JSR memory

Alpha 21264/EV67 Hardware Reference ManualPALcode Restrictions and Guidelines D–13Restriction 22: HW_RET/STALL After HW_MTPR IS0/IS1BIS R31, R31, R31H

D–14 PALcode Restrictions and GuidelinesAlpha 21264/EV67 Hardware Reference ManualRestriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, x

Alpha 21264/EV67 Hardware Reference ManualPALcode Restrictions and Guidelines D–15Restriction 27: Reset of ‘Force-Fail Lock Flag’ State in PALcodeD.23

D–16 PALcode Restrictions and GuidelinesAlpha 21264/EV67 Hardware Reference ManualRestriction 30 : HW_MTPR and HW_MFPR to the Cbox CSRALIGN_FETCH_BLOC

Alpha 21264/EV67 Hardware Reference ManualPALcode Restrictions and Guidelines D–17Restriction 31 : I_CTL[VA_48] Updatesys__cbox_over6: ; block 6beq p6

D–18 PALcode Restrictions and GuidelinesAlpha 21264/EV67 Hardware Reference ManualRestriction 33 : HW_LD Physical/Lock UseD.29 Restriction 33 : HW_LD

Alpha 21264/EV67 Hardware Reference ManualPALcode Restrictions and Guidelines D–19Guideline 39: Writing Multiple DTB Entries in the Same PAL FlowD.35

D–20 PALcode Restrictions and GuidelinesAlpha 21264/EV67 Hardware Reference ManualRestriction 40: Scrubbing a Single-Bit Errorhw_mtpr r31, EV6__DTB_IA

Alpha 21264/EV67 Hardware Reference ManualPALcode Restrictions and Guidelines D–21Restriction 41: MTPR ITB_TAG, MTPR ITB_PTE Must Be in the Same Fetch

2–4 Internal ArchitectureAlpha 21264/EV67 Hardware Reference Manual21264/EV67 MicroarchitectureFigure 2–2 Branch PredictorLocal PredictorThe local pre

D–22 PALcode Restrictions and GuidelinesAlpha 21264/EV67 Hardware Reference ManualRestriction 46: Avoiding Live locks in Speculative Load CRD Handlers

Alpha 21264/EV67 Hardware Reference ManualPALcode Restrictions and Guidelines D–23Restriction 47: Cache Eviction for Single-Bit Cache ErrorsIf "C

D–24 PALcode Restrictions and GuidelinesAlpha 21264/EV67 Hardware Reference ManualRestriction 48: MB Bracketing of Dcache Writes to Force Bad Data ECC

Alpha 21264/EV67 Hardware Reference Manual21264/EV67-to-Bcache Pin Interconnections E–1 E21264/EV67-to-Bcache Pin InterconnectionsThis appendix provid

E–2 21264/EV67-to-Bcache Pin InterconnectionsAlpha 21264/EV67 Hardware Reference ManualLate-Write Non-Bursting SSRAMsE.2 Late-Write Non-Bursting SSRAM

Alpha 21264/EV67 Hardware Reference Manual21264/EV67-to-Bcache Pin Interconnections E–3Dual-Data Rate SSRAMsE.3 Dual-Data Rate SSRAMsTable E–4 provide

E–4 21264/EV67-to-Bcache Pin InterconnectionsAlpha 21264/EV67 Hardware Reference ManualDual-Data Rate SSRAMsFrom board, pulled up to VDD TMS_HFrom boa

Alpha 21264/EV67 Hardware Reference Manual Glossary–1 GlossaryThis glossary

Glossary–2Alpha 21264/EV67 Hardware Reference Manualasynchronous system trap (AST)A software-simulated interrupt to a user-defined routine. ASTs enabl

Alpha 21264/EV67 Hardware Reference Manual Glossary–3bootShort for bootstra

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–521264/EV67 MicroarchitectureFigure 2–4 Global PredictorChoice PredictorThe choice p

Glossary–4Alpha 21264/EV67 Hardware Reference Manualcache hitThe status returned when a logic unit probes a cache memory and finds a valid cache entry

Alpha 21264/EV67 Hardware Reference Manual Glossary–5clock offset (or clkof

Glossary–6Alpha 21264/EV67 Hardware Reference Manualdirect-mapping cacheA cache organization in which only one address comparison is needed to locate

Alpha 21264/EV67 Hardware Reference Manual Glossary–7external cacheSee seco

Glossary–8Alpha 21264/EV67 Hardware Reference Manualof the clock forward logic. Additionally, the framing clock can have a period that is less than,

Alpha 21264/EV67 Hardware Reference Manual Glossary–9interface resetA synch

Glossary–10Alpha 21264/EV67 Hardware Reference Manualmachine checkAn operating system action triggered by certain system hardware-detected errors that

Alpha 21264/EV67 Hardware Reference Manual Glossary–11MSIMedium-scale integ

Glossary–12Alpha 21264/EV67 Hardware Reference Manualoutput mux counterCounter used to select the output mux that drives address and data. It is reset

Alpha 21264/EV67 Hardware Reference Manual Glossary–13PQFPPlastic quad flat

2–6 Internal ArchitectureAlpha 21264/EV67 Hardware Reference Manual21264/EV67 Microarchitecture2.1.1.4 Instruction Fetch LogicThe instruction prefetch

Glossary–14Alpha 21264/EV67 Hardware Reference Manualread stream buffersArrangement whereby each memory module independently prefetches DRAM data prio

Alpha 21264/EV67 Hardware Reference Manual Glossary–15SDRAMSynchronous dyna

Glossary–16Alpha 21264/EV67 Hardware Reference ManualSTRAMSelf-timed random-access memory.superpipelinedDescribes a pipelined machine that has a large

Alpha 21264/EV67 Hardware Reference Manual Glossary–17UNPREDICTABLEResults

Glossary–18Alpha 21264/EV67 Hardware Reference ManualWARWrite-after-read.wordTwo contiguous bytes (16 bits) starting on an arbitrary byte boundary. Th

Alpha 21264/EV67 Hardware Reference ManualIndex–1Index Numerics21264/EV67, features of, 1–332_BYTE_IO Cbox CSRdefined, 5–34AAbbreviations, xixbinary m

Index–2Alpha 21264/EV67 Hardware Reference ManualBC_SJ_BANK_ENABLE Cbox CSRdefined, 5–34BC_TAG_DDM_FALL_EN Cbox CSR, 4–47defined, 5–35BC_TAG_DDM_RISE_

Alpha 21264/EV67 Hardware Reference ManualIndex–3Cboxdata register C_DATA, 5–33described, 2–11, 4–3duplicate Dcache tag array, 2–11duplicate Dcache ta

Index–4Alpha 21264/EV67 Hardware Reference ManualDcachedescribed, 2–12duplicate tag parity errors, 8–4duplicate tags with, 4–13error case summary for,

Alpha 21264/EV67 Hardware Reference ManualIndex–5ECC64-bit data and check bit code, 8–2Dcache data single-bit correctable errors, 8–3for system data b

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–721264/EV67 Microarchitecture• Integer operate• Integer conditional branch• Uncondit

Index–6Alpha 21264/EV67 Hardware Reference ManualI_CTL Ibox control register, 5–15after fault reset, 7–8after warm reset, 7–11at power-on reset state,

Alpha 21264/EV67 Hardware Reference ManualIndex–72–16Integer execution unit. See EboxInteger issue queue, 2–6pipelined, 2–15Internal processor registe

Index–8Alpha 21264/EV67 Hardware Reference ManualMB, 21264/EV67 command, 4–13, 4–21MB_CNT Cbox CSR, operation, 2–32MBDone, SysDc command, 4–13MboxDcac

Alpha 21264/EV67 Hardware Reference ManualIndex–9PALcodeconditional branches in, D–14described, 6–1entries points for, 6–12exception entry points, 6–1

Index–10Alpha 21264/EV67 Hardware Reference ManualReadBlk, 21264/EV67 command, 4–21system probes, with, 4–41ReadBlkI, 21264/EV67 command, 4–22ReadBlkM

Alpha 21264/EV67 Hardware Reference ManualIndex–11Store instructionsDcache ECC errors with, 8–4I/O address space, 2–29I/O reference ordering, 2–31Mbox

Index–12Alpha 21264/EV67 Hardware Reference ManualTrapsload-load order, 2–32Mbox order, 2–31replay, 2–31store-load order, 2–32Trst_L signal pin, 3–6UU

2–8 Internal ArchitectureAlpha 21264/EV67 Hardware Reference Manual21264/EV67 MicroarchitectureThe FQ arbiters pick between simultaneous requesters of

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–921264/EV67 MicroarchitectureFigure 2–6 Integer Execution Unit—Clusters 0 and 1Most

2–10 Internal ArchitectureAlpha 21264/EV67 Hardware Reference Manual21264/EV67 MicroarchitectureThe Ebox has 80 register-file entries that contain sto

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–1121264/EV67 MicroarchitectureThe Fbox register file contains six reads ports and fo

ivAlpha 21264/EV67 Hardware Reference Manual2.3.1 Instruction Group Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–12 Internal ArchitectureAlpha 21264/EV67 Hardware Reference Manual21264/EV67 Microarchitecture• Virtual tag bits [47:15]• 8-bit address space number

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–13Pipeline Organization• Miss address file (MAF)• Dstream translation buffer (DTB)2.

2–14 Internal ArchitectureAlpha 21264/EV67 Hardware Reference ManualPipeline OrganizationFigure 2–8 Pipeline OrganizationStage 0 — Instruction FetchTh

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–15Pipeline OrganizationIn the slot stage, the branch predictor compares the next Ica

2–16 Internal ArchitectureAlpha 21264/EV67 Hardware Reference ManualInstruction Issue RulesStage 4 — Register ReadInstructions issued from the issue q

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–17Instruction Issue Rules2.3.1 Instruction Group DefinitionsTable 2–2 lists the inst

2–18 Internal ArchitectureAlpha 21264/EV67 Hardware Reference ManualInstruction Issue Rules2.3.2 Ebox SlottingInstructions that are issued from the IQ

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–19Instruction Issue RulesE L U U L L U U U E L E U L L U E U E E L U L U U E L

2–20 Internal ArchitectureAlpha 21264/EV67 Hardware Reference ManualInstruction Issue Rules2.3.3 Instruction LatenciesAfter an instruction is placed i

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–21Instruction Retire Rules2.4 Instruction Retire RulesAn instruction is retired when

Alpha 21264/EV67 Hardware Reference Manualv4.3.2 System Duplicate Tag Stores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–22 Internal ArchitectureAlpha 21264/EV67 Hardware Reference ManualRetire of Operate Instructions into R31/F312.4.1 Floating-Point Divide/Square Root

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–23Load Instructions to R31 and F312.6 Load Instructions to R31 and F31This section d

2–24 Internal ArchitectureAlpha 21264/EV67 Hardware Reference ManualSpecial Cases of Alpha Instruction Execution2.6.3 Prefetch, Evict Next: LDQ and HW

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–25Special Cases of Alpha Instruction ExecutionFigure 2–9 Pipeline Timing for Integer

2–26 Internal ArchitectureAlpha 21264/EV67 Hardware Reference ManualSpecial Cases of Alpha Instruction ExecutionFigure 2–10 Pipeline Timing for Floati

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–27Memory and I/O Address Space InstructionsThe first instruction, CMOV1, tests the v

2–28 Internal ArchitectureAlpha 21264/EV67 Hardware Reference ManualMemory and I/O Address Space InstructionsIf the requested physical location is fou

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–29Memory and I/O Address Space Instructions2.8.3 Memory Address Space Store Instruct

2–30 Internal ArchitectureAlpha 21264/EV67 Hardware Reference ManualMAF Memory Address Space Merging Rules• Byte/word store instructions and different

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–31Replay TrapsThe 21264/EV67 maintains the default memory data instruction ordering

viAlpha 21264/EV67 Hardware Reference Manual5.1.3 Virtual Address Register – VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–32 Internal ArchitectureAlpha 21264/EV67 Hardware Reference ManualI/O Write Buffer and the WMB Instruction2.11.1.1 Load-Load Order TrapThe Mbox ensu

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–33I/O Write Buffer and the WMB Instruction• RdBlkSpec (valid), RdBlkModSpec (valid),

2–34 Internal ArchitectureAlpha 21264/EV67 Hardware Reference ManualI/O Write Buffer and the WMB InstructionBecause the MB instruction is executed spe

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–35I/O Write Buffer and the WMB InstructionAlso consider the related sequence shown i

2–36 Internal ArchitectureAlpha 21264/EV67 Hardware Reference ManualPerformance Measurement Support—Performance Counters2.13 Performance Measurement S

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–37Floating-Point Control RegisterUNFD [61] RW Underflow Disable. The 21264/EV67 har

2–38 Internal ArchitectureAlpha 21264/EV67 Hardware Reference ManualAMASK and IMPLVER Instruction Values2.15 AMASK and IMPLVER Instruction ValuesThe A

Alpha 21264/EV67 Hardware Reference ManualInternal Architecture 2–39Design Examples2.16 Design ExamplesThe 21264/EV67 can be designed into many differ

2–40 Internal ArchitectureAlpha 21264/EV67 Hardware Reference ManualDesign ExamplesFigure 2–13 Typical Multiprocessor Configuration64-bit PCI Bus64-bi

Alpha 21264/EV67 Hardware Reference ManualHardware Interface 3–1 3Hardware InterfaceThis chapter contains the 21264/EV67 microprocessor logic symbol a

Alpha 21264/EV67 Hardware Reference Manualvii6.5.2 Hardware Structure of Explicitly Written IPRs . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Hardware InterfaceAlpha 21264/EV67 Hardware Reference Manual21264/EV67 Microprocessor Logic SymbolFigure 3–1 21264/EV67 Microprocessor Logic Symbo

Alpha 21264/EV67 Hardware Reference ManualHardware Interface 3–321264/EV67 Signal Names and Functions3.2 21264/EV67 Signal Names and FunctionsTable 3–

3–4 Hardware InterfaceAlpha 21264/EV67 Hardware Reference Manual21264/EV67 Signal Names and FunctionsBcDataOutClk_H[3:0]BcDataOutClk_L[3:0]O_PP 8 Bcac

Alpha 21264/EV67 Hardware Reference ManualHardware Interface 3–521264/EV67 Signal Names and FunctionsFrameClk_HFrameClk_LI_DA_CLK 2 A skew-controlled

3–6 Hardware InterfaceAlpha 21264/EV67 Hardware Reference Manual21264/EV67 Signal Names and FunctionsTable 3–3 lists signals by function and provides

Alpha 21264/EV67 Hardware Reference ManualHardware Interface 3–721264/EV67 Signal Names and FunctionsBcVref I_DC_REF 1 Tag data input reference voltag

3–8 Hardware InterfaceAlpha 21264/EV67 Hardware Reference ManualPin Assignments3.3 Pin AssignmentsThe 21264/EV67 package has 587 pins aligned in a

Alpha 21264/EV67 Hardware Reference ManualHardware Interface 3–9Pin AssignmentsBcData_H_106 L45 BcData_H_107 N45 BcData_H_108 T44BcData_H_109 U45 BcDa

3–10 Hardware InterfaceAlpha 21264/EV67 Hardware Reference ManualPin AssignmentsBcData_H_9 K2 BcData_H_90 BA3 BcData_H_91 BC3BcData_H_92 BD6 BcData_H_

Alpha 21264/EV67 Hardware Reference ManualHardware Interface 3–11Pin AssignmentsSysAddIn_L_5 BA27 SysAddIn_L_6 BD28 SysAddIn_L_7 BE27SysAddIn_L_8 AY 2

viiiAlpha 21264/EV67 Hardware Reference Manual7.11.2 PLL Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–12 Hardware InterfaceAlpha 21264/EV67 Hardware Reference ManualPin AssignmentsSysDataOutClk_L_5 R41 SysDataOutClk_L_6 AH40 SysDataOutClk_L_7 AW39Sys

Alpha 21264/EV67 Hardware Reference ManualHardware Interface 3–13Pin AssignmentsAR1 BcData_H_22 AR3 Spare AR39 SysData_L_58AR43 BcDataOutClk_H_3 AR45

3–14 Hardware InterfaceAlpha 21264/EV67 Hardware Reference ManualPin AssignmentsBC25 SysAddIn_L_9 BC29 SysAddIn_L_1 BC3 BcData_H_91BC31 SysAddOut_L_12

Alpha 21264/EV67 Hardware Reference ManualHardware Interface 3–15Pin Assignments G39 SysData_L_37 G41 BcData_H_38 G45 BcData_H_104G5 BcData_H_70 G7 Sy

3–16 Hardware InterfaceAlpha 21264/EV67 Hardware Reference ManualPin AssignmentsTable 3–6 lists the 21264/EV67 ground and power (VSS and VDD, respecti

Alpha 21264/EV67 Hardware Reference ManualHardware Interface 3–17Mechanical Specifications3.4 Mechanical SpecificationsThis section shows the 21264

3–18 Hardware InterfaceAlpha 21264/EV67 Hardware Reference Manual21264/EV67 Packaging3.5 21264/EV67 PackagingFigure 3–3 shows the 21264/EV67 pinout

Alpha 21264/EV67 Hardware Reference ManualHardware Interface 3–1921264/EV67 PackagingFigure 3–4 shows the 21264/EV67 pinout from the bottom view with

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–1 4Cache and External InterfacesThis chapter describes the 21264/EV67 cache

Alpha 21264/EV67 Hardware Reference Manualix11.5.2 SROM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualIntroduction to the External Interfaces• The Bcache interface includes a 12

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–3Introduction to the External InterfacesFigure 4–1 21264/EV67 System and Bca

4–4 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualPhysical Address Considerations4.1.1.1 Commands and AddressesThe system sen

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–5Physical Address ConsiderationsPrefetches (LDL, LDF, LDG, LDT, LDBU, LDWU)

4–6 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualPhysical Address ConsiderationsTable 4–1 notes:1. Set Dirty Flow: Based on

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–7Bcache Structure4.3 Bcache StructureThe 21264/EV67 Cbox provides control si

4–8 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualVictim Data Buffer• Issuing probes and SysDc fill commands to the 21264/EV6

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–9Cache CoherencyFigure 4–3 Cache Subset HierarchyThe following tasks must be

4–10 Cache and External InterfacesAlpha 21264/EV67 Hardware Reference ManualCache Coherency4.5.3 Cache Block State TransitionsCache block state transi

Alpha 21264/EV67 Hardware Reference ManualCache and External Interfaces 4–11Cache Coherency4.5.4 Using SysDc CommandsNote the following:• The conventi