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Technical Reference Guide
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
viii
LIST OF FIGURES
F
IGURE
2–1. C
OMPAQ
D
ESKPRO
4000S P
ERSONAL
C
OMPUTER WITH
M
ONITOR
....................................... 2-1
F
IGURE
2–2. C
ABINET
L
AYOUT
, F
RONT
V
IEW
....................................................................................... 2-4
F
IGURE
2–3. C
ABINET
L
AYOUT
, R
EAR
V
IEW
......................................................................................... 2-5
F
IGURE
2–4. C
HASSIS
L
AYOUT
, T
OP
V
IEW
............................................................................................ 2-6
F
IGURE
2–5. S
YSTEM
B
OARD
L
AYOUT
, C
OMPONENT
S
IDE
..................................................................... 2-7
F
IGURE
2–6. C
OMPAQ
D
ESKPRO
4000N
AND
4000S S
YSTEM
A
RCHITECTURE
, B
LOCK DIAGRAM
.............. 2-9
F
IGURE
2–7. M
ICROPROCESSOR
A
RCHITECTURAL
D
IAGRAM
................................................................ 2-10
F
IGURE
3–1. P
ROCESSOR
/M
EMORY
S
UBSYSTEM
A
RCHITECTURE
............................................................ 3-2
F
IGURE
3–2. P
ENTIUM
MMX M
ICROPROCESSOR
I
NTERNAL
A
RCHITECTURE
........................................... 3-3
F
IGURE
3–3. S
YSTEM
M
EMORY
M
AP
....................................................................................................... 3-7
F
IGURE
4–1. PCI B
US
D
EVICES AND
F
UNCTIONS
..................................................................................... 4-2
F
IGURE
4–2. 32-B
IT
PCI B
US
C
ONNECTOR
(32-B
IT
T
YPE
) ..................................................................... 4-3
F
IGURE
4–3. T
YPE
0 C
ONFIGURATION
C
YCLE
........................................................................................ 4-6
F
IGURE
4–4. PCI C
ONFIGURATION
S
PACE
M
AP
...................................................................................... 4-7
F
IGURE
4–5. ISA B
US
B
LOCK
D
IAGRAM
................................................................................................ 4-11
F
IGURE
4–6. ISA E
XPANSION
C
ONNECTOR
.......................................................................................... 4-12
F
IGURE
4–7. M
ASKABLE
I
NTERRUPT
P
ROCESSING
, B
LOCK
D
IAGRAM
.................................................... 4-18
F
IGURE
4–8. C
ONFIGURATION
M
EMORY
M
AP
...................................................................................... 4-24
F
IGURE
5–1. 40-P
IN
IDE C
ONNECTOR
. ................................................................................................. 5-8
F
IGURE
5–1. 50-P
IN
IDE C
ONNECTOR
. ................................................................................................. 5-9
F
IGURE
5–2. 34-P
IN
D
ISKETTE
D
RIVE
C
ONNECTOR
.............................................................................. 5-14
F
IGURE
5–3. S
ERIAL
I
NTERFACES
B
LOCK
D
IAGRAM
............................................................................. 5-15
F
IGURE
5–4. S
ERIAL
I
NTERFACE
C
ONNECTOR
(M
ALE
DB-9
AS VIEWED FROM REAR OF CHASSIS
) ........... 5-15
F
IGURE
5–5. P
ARALLEL
I
NTERFACE
C
ONNECTOR
(F
EMALE
DB-25
AS VIEWED FROM REAR OF CHASSIS
).. 5-27
F
IGURE
5–6. 8042-T
O
-K
EYBOARD
T
RANSMISSION OF
C
ODE
ED
H
, T
IMING
D
IAGRAM
............................ 5-28
F
IGURE
5–7. K
EYBOARD OR
P
OINTING
D
EVICE
I
NTERFACE
C
ONNECTOR
............................................... 5-34
F
IGURE
5–8. E
THERNET
I
NTERFACE
B
LOCK
D
IAGRAM
......................................................................... 5-35
F
IGURE
5–9. E
THERNET
AUI C
ONNECTOR
(DB-15,
VIEWED FROM REAR
) ............................................. 5-36
F
IGURE
5–10. E
THERNET
RJ-45 C
ONNECTOR
...................................................................................... 5-36
F
IGURE
5–11. U
NIVERSAL
S
ERIAL
B
US
C
ONNECTOR
(
ONE OF TWO AS VIEWED FROM REAR OF CHASSIS
)... 5-38
F
IGURE
6–1. S3 T
RIO
64V2/GX-B
ASED
G
RAPHICS
S
UBSYSTEM
, B
LOCK DIAGRAM
................................... 6-2
F
IGURE
6–2. VGA M
ONITOR
C
ONNECTOR
, (F
EMALE
DB-15,
AS VIEWED FROM THE REAR OF CHASSIS
). ... 6-6
F
IGURE
7–1. P
OWER
S
UPPLY
A
SSEMBLY
, B
LOCK
D
IAGRAM
.................................................................... 7-1
F
IGURE
7–2. P
OWER
C
ABLE
D
IAGRAM
.................................................................................................. 7-4
F
IGURE
7–3. L
OW
V
OLTAGE
S
UPPLY
, B
LOCK
D
IAGRAM
......................................................................... 7-5
F
IGURE
7–4. S
IGNAL
D
ISTRIBUTION
D
IAGRAM
....................................................................................... 7-6
F
IGURE
C–1. K
EYSTROKE
P
ROCESSING
E
LEMENTS
, B
LOCK
D
IAGRAM
....................................................C-2
F
IGURE
C–2. K
EYBOARD
-T
O
-S
YSTEM
T
RANSMISSION OF
C
ODE
58
H
, T
IMING
D
IAGRAM
..........................C-3
F
IGURE
C–3. U.S. E
NGLISH
(101-K
EY
) K
EYBOARD
K
EY
P
OSITIONS
.......................................................C-4
F
IGURE
C–4. N
ATIONAL
(102-K
EY
) K
EYBOARD
K
EY
P
OSITIONS
............................................................C-4
F
IGURE
C–5. U.S. E
NGLISH
W
INDOWS
(101W-K
EY
) K
EYBOARD
K
EY
P
OSITIONS
...................................C-5
F
IGURE
C–6. N
ATIONAL
W
INDOWS
(102W-K
EY
) K
EYBOARD
K
EY
P
OSITIONS
........................................C-5
F
IGURE
C–7. U.S. E
NGLISH
W
INDOWS
(101WE-K
EY
) K
EYBOARD
K
EY
P
OSITIONS
.................................C-6
F
IGURE
C–8. N
ATIONAL
W
INDOWS
(102WE-K
EY
) K
EYBOARD
K
EY
P
OSITIONS
......................................C-6
F
IGURE
C–9. S
CANNER
E
LEMENTS
, B
LOCK
D
IAGRAM
..........................................................................C-14
F
IGURE
C–10. S
CANNER OPERATION
F
LOW
C
HART
..............................................................................C-16
- Technical 1
- Reference 1
- Technical Reference Guide 4
- TABLE OF CONTENTS 5
- LIST OF FIGURES 10
- LIST OF TABLES 11
- Chapter 1 13
- INTRODUCTION 13
- Continued 15
- Chapter 2 19
- SYSTEM OVERVIEW 19
- 2.2 FEATURES 20
- 2.2.1 STANDARD FEATURES 20
- 2.2.2 MODEL DIFFERENCES 21
- 2.2.3 OPTIONS 21
- 2.3 MECHANICAL DESIGN 22
- 2.3.1 CABINET LAYOUT 22
- 2.3.2 CHASSIS LAYOUT 24
- 2.3.3 SYSTEM BOARD LAYOUT 25
- 2.4 SYSTEM ARCHITECTURE 26
- 2.4.1 MICROPROCESSOR 28
- 2.4.2 MEMORY 28
- 2.4.3 SUPPORT CHIPSET 29
- 2.4.4 MASS STORAGE 29
- 2.4.7 GRAPHICS SUBSYSTEM 30
- 2.5 SPECIFICATIONS 31
- Chapter 2 System Overview 34
- Chapter 3 35
- PROCESSOR/ 35
- MEMORY SUBSYSTEM 35
- 3.2.1.1 MMX Technology 37
- 3.2.4 SYSTEM MEMORY 39
- Chapter 4 43
- SYSTEM SUPPORT 43
- 4.2 PCI BUS OVERVIEW 44
- 4.2.1 PCI CONNECTOR 45
- 4.2.3 PCI BUS TRANSACTIONS 47
- 4.2.3.2 Configuration Cycles 47
- 4.2.5 PCI INTERRUPT MAPPING 51
- 4.2.6 PCI CONFIGURATION 52
- 4.3 ISA BUS OVERVIEW 53
- 4.3.1 ISA CONNECTOR 54
- 4.3.2 ISA BUS TRANSACTIONS 55
- 4.3.3 DIRECT MEMORY ACCESS 57
- 4.3.3.1 Page Registers 58
- 4.3.4 INTERRUPTS 60
- 4.3.4.1 Maskable Interrupts 60
- NMI- Generation 62
- SMI- Generation 63
- 4.3.5 INTERVAL TIMER 64
- 4.3.6 ISA CONFIGURATION 64
- Chapter 4 System Support 82
- 4.6.1 SYSTEM I/O MAP 83
- 4.7.2 PASSWORD PROTECTION 87
- 4.7.3 I/O SECURITY 88
- 4.7.4 USER SECURITY 88
- 4.7.5 TEMPERATURE SENSING 89
- 4.7.6 POWER MANAGEMENT 90
- Chapter 5 91
- INPUT/OUTPUT INTERFACES 91
- 5.2.2 IDE CONNECTORS 98
- 5.3 DISKETTE DRIVE INTERFACE 100
- 5.4 SERIAL INTERFACES 105
- 5.4.1 RS-232 INTERFACE 105
- 5.5 PARALLEL INTERFACE 111
- 5.6.3.1 8042 Configuration 120
- 5.6.3.2 8042 Control 121
- Continued 122
- (Continued) 123
- 1 DATA Data 4 + 5 VDC Power 124
- 5.7 ETHERNET INTERFACE 125
- 5.7.2 NIC CONNECTORS 126
- 5.8.1 USB CONFIGURATION 127
- 5.8.2 USB CONTROL 128
- 5.8.3 USB CONNECTOR 128
- Chapter 6 129
- GRAPHICS SUBSYSTEM 129
- 6.2 SUBSYSTEM DESCRIPTION 130
- 6.2.3.2 Subsystem Control 132
- MONITOR POWER CONTROL 133
- 6.2.5 CONNECTORS 134
- Chapter 7 135
- POWER and SIGNAL 135
- DISTRIBUTION 135
- 7.2.1 POWER SUPPLY ASSEMBLY 136
- 7.2.2 POWER CONTROL 137
- 7.3 POWER DISTRIBUTION 138
- 7.4 SIGNAL DISTRIBUTION 140
- Chapter 8 141
- BIOS ROM 141
- 8.2 BOOT FUNCTIONS 142
- 8.2.1 BOOT BLOCK 142
- 8.2.2 QUICKBOOT 142
- 8.2.3 SILENTBOOT 142
- ACCESSING CMOS 143
- SETTING DEFAULT PARAMETERS 143
- 8.4.1 SYSTEM ID 147
- Chapter 8 BIOS ROM 148
- Technical Reference Guide 149
- 8.4.3 TEMPERATURE SENSOR 152
- 8.4.4 DRIVE FAULT PREDICTION 152
- 8.4.5 DIMM SUPPORT 153
- 8.4.6 SECURITY FUNCTIONS 155
- 8.5 PNP SUPPORT 157
- 8.6 POWER MANAGEMENT SUPPORT 158
- Appendix A 161
- ERROR MESSAGES AND CODES 161
- Appendix B 173
- ASCII CHARACTER SET 173
- Appendix C 175
- KEYBOARD 175
- C.2 KEYSTROKE PROCESSING 176
- C.2.2 KEYBOARD LAYOUTS 178
- C.2.3 KEYS 181
- Changed - November 1996 182
- C.2.3.3 Windows Keystrokes 183
- C.2.4 KEYBOARD COMMANDS 184
- C.2.5 SCAN CODES 184
- C.3 SCANNER DESCRIPTION 188
- C.3.1 SCANNER OPERATION 189
- Appendix C Keyboard 190
- Compaq Personal Computers 190
- C.3.1.2 Image Quality 191
- C.3.2 SCANNER INTERFACE 192
- C.3.2.1 Pnyb Mode 193
- First Edition – July 1997 195
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