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Technical Reference Guide
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
5-35
5.7 ETHERNET INTERFACE
The system board integrates an Ethernet interface that supports both 10 and 100 Mbps Ethernet
communications using IEEE 802.3 (ISO 8802-3) protocol. Two connection options are available;
an RJ-45 jack for twisted-pair Ethernet (TPE) systems (10BaseT and 100BaseTX) and an AUI
connector for a direct 10BaseT connection or to a 10Base2 connection through and AUI-to-BNC
adapter. The Ethernet interface (Figure 5-9) is based on the Texas Instruments TLAN3.1
component, which operates off the PCI bus and features auto-switching between 10 and 100 Mb/s
interfaces.
Figure 5–8.
Ethernet Interface Block Diagram
The RJ-45 connctor is the default port, which is the required connection if Remote Wakeup
operation or 10/100 autosensing is desired. Note also that the LED indicators are operational
only for the RJ-45 interface. The LEDs provide the following indications:
Link LED (yellow) - Indicates reception of link pulses in 10 Mbs mode, indicates scrambler lock
and valid idle code reception during 100 Mbs mode.
Active LED (green) - Indicates network activity.
The network interface controller supports Remote Wakeup using the Magic Packet method of
waking up a system unit that is powered down (the NIC logic is powered by +5 AUX, which is
active as long as the system is receiving AC line voltage). With Remote Wakeup feature enabled,
a received Magic Packet results in the PINTA- signal being asserted (low) and routed to power
control logic, which in turn activates the power supply (refer to Chapter 7, “Power and Signal
Distribution” for a discussion of the power control logic).
AUI Connector
TX/RX
RJ-45 Connector
TX/RX
TX/RX
Filter
TLAN3.1
Ethernet
Controller
PCI Bus
TX/RX
+12 VDC
PINTA-
INT Cntlr.
& Power
Control
Lo
g
ic
Filter
PHY
Active
(
Green
)
Link
(
Yellow
)
TX/RX,
Cntrl
- Technical 1
- Reference 1
- Technical Reference Guide 4
- TABLE OF CONTENTS 5
- LIST OF FIGURES 10
- LIST OF TABLES 11
- Chapter 1 13
- INTRODUCTION 13
- Continued 15
- Chapter 2 19
- SYSTEM OVERVIEW 19
- 2.2 FEATURES 20
- 2.2.1 STANDARD FEATURES 20
- 2.2.2 MODEL DIFFERENCES 21
- 2.2.3 OPTIONS 21
- 2.3 MECHANICAL DESIGN 22
- 2.3.1 CABINET LAYOUT 22
- 2.3.2 CHASSIS LAYOUT 24
- 2.3.3 SYSTEM BOARD LAYOUT 25
- 2.4 SYSTEM ARCHITECTURE 26
- 2.4.1 MICROPROCESSOR 28
- 2.4.2 MEMORY 28
- 2.4.3 SUPPORT CHIPSET 29
- 2.4.4 MASS STORAGE 29
- 2.4.7 GRAPHICS SUBSYSTEM 30
- 2.5 SPECIFICATIONS 31
- Chapter 2 System Overview 34
- Chapter 3 35
- PROCESSOR/ 35
- MEMORY SUBSYSTEM 35
- 3.2.1.1 MMX Technology 37
- 3.2.4 SYSTEM MEMORY 39
- Chapter 4 43
- SYSTEM SUPPORT 43
- 4.2 PCI BUS OVERVIEW 44
- 4.2.1 PCI CONNECTOR 45
- 4.2.3 PCI BUS TRANSACTIONS 47
- 4.2.3.2 Configuration Cycles 47
- 4.2.5 PCI INTERRUPT MAPPING 51
- 4.2.6 PCI CONFIGURATION 52
- 4.3 ISA BUS OVERVIEW 53
- 4.3.1 ISA CONNECTOR 54
- 4.3.2 ISA BUS TRANSACTIONS 55
- 4.3.3 DIRECT MEMORY ACCESS 57
- 4.3.3.1 Page Registers 58
- 4.3.4 INTERRUPTS 60
- 4.3.4.1 Maskable Interrupts 60
- NMI- Generation 62
- SMI- Generation 63
- 4.3.5 INTERVAL TIMER 64
- 4.3.6 ISA CONFIGURATION 64
- Chapter 4 System Support 82
- 4.6.1 SYSTEM I/O MAP 83
- 4.7.2 PASSWORD PROTECTION 87
- 4.7.3 I/O SECURITY 88
- 4.7.4 USER SECURITY 88
- 4.7.5 TEMPERATURE SENSING 89
- 4.7.6 POWER MANAGEMENT 90
- Chapter 5 91
- INPUT/OUTPUT INTERFACES 91
- 5.2.2 IDE CONNECTORS 98
- 5.3 DISKETTE DRIVE INTERFACE 100
- 5.4 SERIAL INTERFACES 105
- 5.4.1 RS-232 INTERFACE 105
- 5.5 PARALLEL INTERFACE 111
- 5.6.3.1 8042 Configuration 120
- 5.6.3.2 8042 Control 121
- Continued 122
- (Continued) 123
- 1 DATA Data 4 + 5 VDC Power 124
- 5.7 ETHERNET INTERFACE 125
- 5.7.2 NIC CONNECTORS 126
- 5.8.1 USB CONFIGURATION 127
- 5.8.2 USB CONTROL 128
- 5.8.3 USB CONNECTOR 128
- Chapter 6 129
- GRAPHICS SUBSYSTEM 129
- 6.2 SUBSYSTEM DESCRIPTION 130
- 6.2.3.2 Subsystem Control 132
- MONITOR POWER CONTROL 133
- 6.2.5 CONNECTORS 134
- Chapter 7 135
- POWER and SIGNAL 135
- DISTRIBUTION 135
- 7.2.1 POWER SUPPLY ASSEMBLY 136
- 7.2.2 POWER CONTROL 137
- 7.3 POWER DISTRIBUTION 138
- 7.4 SIGNAL DISTRIBUTION 140
- Chapter 8 141
- BIOS ROM 141
- 8.2 BOOT FUNCTIONS 142
- 8.2.1 BOOT BLOCK 142
- 8.2.2 QUICKBOOT 142
- 8.2.3 SILENTBOOT 142
- ACCESSING CMOS 143
- SETTING DEFAULT PARAMETERS 143
- 8.4.1 SYSTEM ID 147
- Chapter 8 BIOS ROM 148
- Technical Reference Guide 149
- 8.4.3 TEMPERATURE SENSOR 152
- 8.4.4 DRIVE FAULT PREDICTION 152
- 8.4.5 DIMM SUPPORT 153
- 8.4.6 SECURITY FUNCTIONS 155
- 8.5 PNP SUPPORT 157
- 8.6 POWER MANAGEMENT SUPPORT 158
- Appendix A 161
- ERROR MESSAGES AND CODES 161
- Appendix B 173
- ASCII CHARACTER SET 173
- Appendix C 175
- KEYBOARD 175
- C.2 KEYSTROKE PROCESSING 176
- C.2.2 KEYBOARD LAYOUTS 178
- C.2.3 KEYS 181
- Changed - November 1996 182
- C.2.3.3 Windows Keystrokes 183
- C.2.4 KEYBOARD COMMANDS 184
- C.2.5 SCAN CODES 184
- C.3 SCANNER DESCRIPTION 188
- C.3.1 SCANNER OPERATION 189
- Appendix C Keyboard 190
- Compaq Personal Computers 190
- C.3.1.2 Image Quality 191
- C.3.2 SCANNER INTERFACE 192
- C.3.2.1 Pnyb Mode 193
- First Edition – July 1997 195
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